Abstract:Aiming at the issue of garbled data during synchronous acquisition caused by inconsistent timing delays in multi-channel high-speed serial signals, this paper proposes a universal algorithm for picosecond-level timing phase adjustment. This algorithm utilizes the internal delay units of an FPGA to achieve picosecond-level delay alignment and extends the delay range through the cascading of multi-level delay units. By incorporating layout and routing constraints, it ensures that the cascaded delay modules are closely arranged in physical space, thereby achieving picosecond-level precision delays within the nanosecond range. Additionally, by adjusting the phase of the FPGA sampling clock to match the signal pulse width and building upon an adaptive word alignment algorithm, the algorithm enables correct sampling of multi-channel high-speed serial signals. Finally, the effectiveness of the algorithm is verified through practical application examples, demonstrating its significant engineering value in the acquisition of multi-channel high-speed serial signals.