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DOI:
飞控与探测:2025,8(1):77-88
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一种基于共享DDR的多核异构数据高速交互方法
(南京理工大学 机械工程学院)
A High-Speed Data Interaction Method for Multi-Core Heterogeneous Systems Based on Shared DDR
(School of Mechanical Engineering, Nanjing University of Science and Technology)
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中文摘要: 针对飞行器导航系统中的多源传感器数据交互效率问题,提出了基于共享内存的多核处理器高速数据交互方法,设计了高速数据传输通道和OpenAMP架构的异构多核数据通信方案,解决了数据信号读取与交互中实时(高速)性、可靠性问题。从硬件上,设计了可编程逻辑部分的系统链路连接方式,并采用AXI DMA控制器实现向DDR存储器的高速数据写入。通过SoC中的两片Cortex-A9处理器分别运行裸机程序和Linux系统,基于RPMsg协议实现了多核处理器之间的数据大量交互。经过实际操作与测试验证,在系统时钟频率最高为100MHz,单次数据传输量最大达到10000×4 B时,FPGA向DDR存储器写入数据的速度可达到244 MB/s,实现了大规模数据的有效交互。
Abstract:Aiming at the problem of multi-source sensor data interaction efficiency in aircraft navigation systems, the paper investigates a high-speed data interaction method for multi-core processors based on shared memory, designing a high-speed data transmission channel and a heterogeneous multi-core data communication scheme using the OpenAMP architecture. This approach resolves issues of real-time (high-speed) performance and reliability in data signal reading and interaction. From a hardware perspective, the paper designs the system link connection method for the programmable logic part and employs an AXI DMA controller to achieve high-speed data writing to DDR memory. By running a bare-metal program and a Linux system on two Cortex-A9 processors within the SoC, extensive data interaction between the multi-core processors is realized based on the RPMsg protocol. Through practical operation and testing, it is verified that at a maximum system clock frequency of 100MHz and a single data transmission volume of up to 10000×4 B, the speed of writing data from the FPGA to DDR memory can reach 244MB/s, achieving efficient large-scale data interaction.
文章编号:20250109     中图分类号:TN702;U666.12+3    文献标志码:A
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黄宇锴,王舒杨,姜波.一种基于共享DDR的多核异构数据高速交互方法[J].飞控与探测,2025,8(1):77-88.